The following abbreviations are utilized herein:
ALD atomic layer deposition
ARC antireflective coating
BEOL back end of line
BoX buried oxide
CD critical dimension
CMOS complementary metal-oxide semiconductor
COO cost of ownership
CVD chemical vapor deposition
FET field effect transistor
HM hardmask
MLD multilayer deposition
NFC near frictionless carbon
OPL organic planarization layer
PC photonic crystal
PD pitch doubling
PECVD plasma enhanced chemical vapor deposition
PR photoresist
RIE reactive ion etch
SOI silicon-on-insulator
SIT sidewall image transfer
STI shallow trench isolation
Photolithography is a technique for transferring an image rendered on one media onto another media photographically. Photolithography techniques are widely used in semiconductor fabrication. Typically, a circuit pattern is rendered as a positive or negative mask image which is then projected onto a silicon substrate coated with photosensitive materials (e.g., PR). Radiation impinges on the masked surface to chemically change those areas of the coating exposed to the radiation, usually by polymerizing the exposed coating. The unpolymerized areas are removed, being more soluble in the developer than the polymerized regions, and the desired image pattern remains.
Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates. The present invention is directed to such micro-sized devices.
Effective lithographic techniques are essential for achieving reduction of feature sizes. Lithography impacts the manufacture of microscopic structures, not only in terms of directly imaging patterns on the desired substrate, but also in terms of making masks typically used in such imaging. Typical lithographic processes involve formation of a patterned resist layer by patternwise exposing a radiation-sensitive resist to an imaging radiation. The image is subsequently developed by contacting the exposed resist layer with a material (typically an aqueous alkaline developer) to selectively remove portions of the resist layer to reveal the desired pattern. The pattern is subsequently transferred to an underlying material by etching the material in openings of the patterned resist layer. After the transfer is complete, the remaining resist layer is removed.
For some lithographic imaging processes, the resist used does not provide sufficient resistance to subsequent etching steps to enable effective transfer of the desired pattern to a layer underlying the resist. In many instances (e.g., where an ultrathin resist layer is desired, where the underlying material to be etched is thick, where a substantial etching depth is required and/or where it is desired to use certain etchants for a given underlying material), a so-called HM layer is used intermediate between the resist layer and the underlying material to be patterned by transfer from the patterned resist. The HM layer receives the pattern from the patterned resist layer and should be able to withstand the etching processes needed to transfer the pattern to the underlying material.
Also, where the underlying material layer is excessively reflective of the imaging radiation used to pattern the resist layer, a thin ARC is typically applied between the underlying layer and the resist layer. In some instances, the ARC and HM functions may be served by a same material. In other cases, an OPL may be used as a softmask. The OPL serves two roles. First, the OPL helps define the depth of focus by ensuring smooth planarization. Second, the OPL acts as an ARC to reduce or prevent reflections of the incident laser beam. Other liquid or viscous films may be utilized instead of an OPL to achieve similar performance. One non-limiting example of an OPL is ODL.
Basically, a FET is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate. More than one gate (multi-gate) can be used to more effectively control the channel. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (i.e., the distance between the source and drain). Multi-gate FETs are considered to be promising candidates to scale CMOS FET technology down to the sub-22 nm regime.
The size of FETs has been successfully reduced through the use of one or more fin-shaped channels. A FET employing such a channel structure may be referred to as a FinFET. Previously, CMOS devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
Device parameters of FinFETs are extremely sensitive to semiconductor fin thickness. In order to realize the full potential of a FinFET, the silicon fin must be very thin (e.g., on the same order of thickness as that of a fully-depleted SOI). Similarly, line width control problems during gate electrode definition for small devices can lead to performance degradation, power consumption control issues and yield loss. Previously, lithographic techniques have been used to form device components (e.g., semiconductor fins for FinFETs, gate electrodes, etc.) in a substrate. For example, using photolithography a feature can be printed directly into a photo-resist layer and the image can be transferred into an underlying film. However, current state-of-the-art lithographic technology cannot adequately and efficiently satisfy the ever-increasing demand for smaller devices and device components. Thus, the requirement for very thin, replicable, device components has re-awakened interest in SIT to form such components.
SIT involves the usage of a sacrificial structure (e.g., a mandrel, typically composed of a polycrystalline silicon). A sidewall spacer (such as silicon dioxide or silicon nitride, Si3N4, for example) having a thickness less than that permitted by the current ground rules is formed on the sides of the mandrel (e.g., via oxidization or film deposition and etching). After removal of the mandrel, the remaining sidewall spacer is used as a HM to etch the layer(s) below, for example, with a directional RIE. Since the sidewall has a (sublithographic) width less than the ground rules, the structure formed in the layer below will also have a sublithographic width. In other uses, the sidewall may be used as a component in the desired structure (e.g., as a portion of the fins in a FinFET).
One exemplary additive SIT process is as follows. A mandrel (e.g., a narrow band) is defined across a hard mask on a substrate. Specifically, a multi-layer stack comprising, for example, a substrate with underlying polysilicon for FET gate patterning, a thin dielectric (e.g., nitride) hard mask layer, a thick mandrel (e.g., a polysilicon) layer, and a mandrel mask layer, is patterned and etched using standard lithographic techniques to form the mandrel with vertical walls above the hard mask layer. Then, spacers are formed on the hard mask adjacent to the walls of the mandrels (e.g., by depositing a thin conformal oxide or nitride layer and performing an anisotropic etch to remove the conformal oxide or nitride layer from the top of the mandrel layer and from horizontal surfaces). The spacer thickness is chosen to be the same as that of the desired width of the final shape (factoring in any etch film erosion). Thus, spacers are formed on the vertical walls of a mandrel and these spacers determine the final pattern widths and tolerances of the components being formed in the substrate. The spacer pattern image created from the walls of the mandrel is then transferred (e.g., by RIE) into the hard mask on the substrate. The hard mask is used to pattern the components (e.g., fins, gates, etc.) in the substrate.
In some cases, the sidewall material may be selected to deposit conformally in order to maintain a desired width and to be etch resistant (i.e., to act as a HM). In some cases, the layer below may be selected to have appropriate electrical properties (e.g., in accordance with the desired product). As a non-limiting example, the layer below may comprise polycrystalline silicon.
Further reference with regards to SIT processes and techniques may be made to commonly-assigned U.S. Pat. No. 7,381,655 to Furukawa et al. and commonly-assigned U.S. Patent Application Publication No. 2007/0066009 by Furukawa et al., both of which are incorporated by reference herein in their entireties.